1. Field of the Invention
The present invention relates generally to logic circuits, and more particularly to logic circuits formed on the same substrate for carrying out a quasi-complementary operation.
2. Description of the Background Art
In recent years, there have been increasing demands for semiconductor integrated logic circuits operable at very high speed with increased noise margin and capable of being highly integrated with lower power consumptions. To satisfy such increasing demands, electronic devices employing a III-V group compound semiconductor such as GaAs in place of conventionally employed silicon are energetically studied and developed.
The following transistor types emaloy GaAs construction: MESFET (Metal Semiconductor Junction FET), HEMT (High Electron Mobility Transistor), HBT (Hetero Junction Bipolar Transistor), RHET (Resonant Hot Electron Transistor), etc. The HEMT, HBT and RHET require advanced process techniques such as epitaxial growth by, e.g., MBE (Molecular Beam Epitaxy), Mo-CVD (Metal organic Chemical Vapor Deposition) etc., Transistor fabrication using these advanced processes are currently under development and are not yet available on a commercial basis. Concerning As for MESFET devices, however, a 16KSRAM and a 30KG gate array and the like have already been presented in a meeting concerned in the field, and products of LSI level are about to be put in practice.
As logic circuits employing GaAs MESFET, various circuit configurations are used such as DCFL (Direct Coupled FET Logic), BFL (Buffered FET Logic), SCFL (Source Coupled FET Logic), LPFL (Low Pinchoff voltage FET Logic) and SDFL (Schottky Diode FET Logic).
An example of the DCFL circuit will now be described with reference to FIG. 10. This circuit comprises DCFL inverter circuits 19a and 19b connected at two stages, each of which includes a load transistor 10 formed of a depletion type MESFET having a drain connected to a first power supply V.sub.DD and a source and a gate connected to each other, and a drive transistor 20 formed of an enhancement type MESFET having a drain connected to a common node of the source and gate of load transistor 10, a source connected to a second power supply GND and a gate provided with an input. At both stages, an output can be derived from the common node of the source and gate of each of load transistors 10.
Since the DCFL has a simple configuration with a small number of elements and operates at the highest speed out of the circuits currently being proposed, it is applied to many logic LSIs as well as memories. The DCFL, however, has a disadvantage that an output high level V.sub.OH is limited to approximately 0.6 V or less of a clamping voltage of a transistor at the succeeding stage. That is, in the MESFET employed in DCFL, since its gate and channel have a Schottky junction which is different from a MOS transistor made of silicon or the like, a current abruptly starts flowing from the gate to source when a source-gate voltage exceeds a clamping voltage which is determined by a gate metal and an impurity concentration. Therefore, the gate-source voltage in the MESFET can not increase beyond the clamping voltage. Thus, an output level of DCFL circuit 19a at the first stage in the circuit of FIG. 10 is limited by the clamping voltage across the source and gate of drive transistor 20 in DCFL circuit 19b at the second stage. Since the clamping voltage across the gate and source of the MESFET is normally at approximately 0.6 V, the output high level VOH is limited to 0.6 V or less. Meanwhile, since an output low level V.sub.OL is approximately 0.1 V, a logic voltage swing V.sub.L becomes approximately 0.5 V.
An ECL circuit employing a silicon bipolar transistor operates with a logic voltage swing V.sub.L being approximately 0.5 V. This is possible because a logic level is determined by employing a highly controllable base-emitter voltage V.sub.BE and a resistance ratio. In the DCFL employing MESFET, a logic level is affected by a gate threshold voltage V.sub.th and a variable parameter such as a current characteristic, and hence it is very difficult to manufacture large-scale integrated circuits in mass production while retaining a sufficient noise margin at approximately 0.5 V of logic voltage swing V.sub.L. Furthermore, although power consumption of DCFL is comparatively low at 0.1 mW-1.0 mW, it is desirable on an LSI basis to further decrease the power consumption with regard to allowable power consumption of chip.
Under such circumstances, a GaAs load current controlled logic circuit (hereinafter referred to as LCCL) is proposed (e.g., in Collected Papers of Electronic Information Communication Meeting 87/2 Vol. J70-D No. 2). FIG. 11 shows an inverter circuit as an example of the LCCL. The LCCL of FIG. 11 comprises a depletion type load transistor 1 having a drain connected to a first power supply V.sub.DD, a drive transistor 2 having a drain connected to a source of load transistor 1, a source connected to a second power supply GND and a gate connected to an input terminal IN. A resistor 3 is connected between a node of the source of load transistor 1 and the drain of drive transistor 2 and a gate of load transistor 1. Load transistor controlling transistor 4 has a drain connected to a node of the gate of load transistor 1 and resistor 3, a source connected to a third power supply V.sub.SS which has a lower voltage than the second power supply GND and a gate connected to the input terminal IN.
This LCCL operates in the following manner. When the input IN is at low level, drive transistor 2 and control transistor 4 are both in OFF state, so that no current flows through resistor 3 and thus a drop voltage in resistor 3 is 0V. Accordingly, a gate-source voltage V.sub.GS in load transistor 1 is 0V at this time. Referring to FIG. 12, output level an V.sub.out becomes a voltage V.sub.OH at an intersection 21 of a load curve (V.sub.GS =0V) shown by the solid line a. An input characteristic of a logic circuit at the succeeding stage (Schottky characteristic of an input transistor, or in detail, Schottky voltage of control transistor 4) is shown by solid line b.
When the input IN is at a high level, drive transistor 2 and control transistor 4 are both in an ON state, so that a current flows through resistor 3 to cause a potential difference between opposite ends thereof. Therefore, the gate-source voltage V.sub.GS of load transistor 1 attains a negative value, so that load transistor 1 attains a near OFF state as shown by the dotted line d of FIG. 12. Thus, the output level V.sub.out at this time becomes a voltage V.sub.OLI at an intersection 22 of a current characteristic of drive transistor 2 shown by the dotted line c and that of load transistor 1 shown by the dotted line d of FIG. 12. It should be noted, however, that load transistor 1 is not completely turned off since a current flows through resistor 3 in this case.
As described in the foregoing, controlling load transistor 1 according to an input level causes the LCCL to perform such a quasi-complementary operation as follows: when the input is at high level, load transistor 1 is almost turned off, while when the input is at low level, drive transistor 2 is completely turned off.
Since the LCCL performs the above described quasi-complementary operation so as to cause little load currents to flow when the input is at high level or low level, it is possible to decrease the power consumption to about a half when compared to the DCFL of FIG. 12.
Further, the DCFL employing GaAs has a disadvantage in that a fluctuation in the characteristic of elements causes frequent eroneous operations; however, in the LCCL, this problem is reduced by the quasi-complementary operation by which a load current is small when the input is at high level.
This point will be described in further detail in the following. An output low level of DCFL is indicated by a voltage V.sub.a2 at an intersection 23 of an I.sub.ds -V.sub.DS characteristic of the drive transistor shown by the dotted line c and that of the load transistor when V.sub.DS =.sub.0V shown by the solid line a, in FIG. 12. Meanwhile, an output low level of LCCL is indicated by a voltage V.sub.OL at an intersection 22 of the dotted line c and the dotted line d showing the I.sub.ds -V.sub.DS characteristic of the load transistor when V.sub.GS is negative biased. Here, a drain-source current I.sub.ds is approximated as follows: EQU I.sub.ds =.beta.(V.sub.GS -V.sub.th).sup.2 . . . (1)
where V.sub.GS is a gate-source voltage, and V.sub.th is a gate threshold voltage.
Assuming that the fluctuation of Vth is .DELTA.V.sub.th where V.sub.th &gt;0, a saturation current I.sub.ds (a) of the characteristic shown by the solid line a is expressed as below: EQU I.sub.ds (a)=.beta.(-V.sub.th).sup.2 . . . (2)
As V.sub.th &lt;0, a fluctuation width .DELTA.I.sub.ds (a) of I.sub.ds (a) is expressed as follows: EQU .DELTA.I.sub.ds (a) =.beta.(-V.sub.th +.DELTA.V.sub.th).sup.2 -.beta.(-V.sub.th -.DELTA.V.sub.th).sup.2 =-4.beta.V.sub.th .DELTA.V.sub.th . . . (3)
Similarly, a saturation current I.sub.ds (d), .DELTA.I.sub.ds (d) with respect to the characteristic shown by the dotted line d is shown below: EQU I.sub.ds (d)=.beta.(V.sub.GS -V.sub.th).sup.2 . . . (4)
.DELTA.I.sub.ds (d)=.beta.(V.sub.GS-V.sub.th +.DELTA.V.sub.th).sup.2 -.beta.(V.sub.GS -V.sub.th -.DELTA.V.sub.th).sup.2 =4.beta.(V.sub.GS -V.sub.th).DELTA.V.sub.th . . . (5)
Further, when a non-saturated portion of the characteristic of the dotted line c is approximated to a straight line, a fluctuation ratio ##EQU1## of the output low level of LCCL to that of DCFL is expressed as follows: ##EQU2## The fluctuation of the output low level of LCCL becomes smaller than that of DCFL. Where V.sub.th= 0.4 V, VGS (LCCL)=-0.3 V, the fluctuation ratio is shown as follows: ##EQU3## As shown above, the fluctuation of low level of LCCL becomes 1/4 that of DCFL. In addition to lower power consumption in comparison with DCFL circuits as described above, LCCL circuits exhibit decreased fluctuation of its low level output.
The LCCL has another characteristic in that the fluctuation Of low level of LCCL is smaller than that of DCFL. The advantage of LCCL is due to the quasi-complementary operation in which little load currents flow when the output is at low level, and hence it is considered that the quasi-complementary operation circuit is effective for enhancing the performance of the GaAs logic circuit. The LCCL, however, has the following disadvantages.
In the conventional logic circuit, as described above, the source of the control transistor is terminated by the third power suppl V.sub.SS which has a lower potential than that of the second power supply level, i.e., lower than GND potential. Therefore, the input high level is clamped with a voltage which is lower than that in case of an DCFL circuit. The reason why the source of control transistor 4 is terminated by V.sub.SS having a lower potential than GND is that when the input is at high level, the drain of control transistor 4 has a lower potential than the drain of drive transistor 2 due to a voltage drop in resistor 3. However, a current is also required to flow through control transistor 4 at this time. Even if a depletion type transistor is employed as control transistor 4, the source of control transistor 4 must not be connected to GND since V.sub.DS must be greater than zero. Thus, it is impossible to avoid the decrease in V.sub.OH due to the termination of the source of control transistor 4 by V.sub.SS.
In addition, since the gate of drive transistor 2 and that of control transistor 4 are connected in parallel, a load capacitance is increased with respect to a logic output at the preceding stage, thereby preventing fast circuit switching operation. Moreover, while FIG. 11 shows the inverter circuit, as the number of inputs is increased such as 2 NOR, for example, the number of control transistors 4 and drive transistors 2 must also be increased, resulting in a degradation in degrees of integration.